The present invention relates to edge rate control circuits generally, and, more particularly, to a method and/or apparatus for controlling the edge rate of low voltage differential signals, particularly at high frequencies.
Referring to FIG. 1, a circuit 10 is shown implementing a conventional edge rate control circuit. The edge rate control of the circuit 10 is achieved by adding N parallel switches driven by a multi-phase clock through flip flops. The timing between the first and last clock phase determines the edge rates of the transmitted differential waveforms. The flip flops are used to synchronize the timing between V+ and Vxe2x88x92 and can also be used to synchronize between two or more buffers.
Referring to FIG. 2, a circuit 30 is shown implementing a conventional multi-phase clock generation circuit. A number of clock signals Clock less than 1 greater than  to Clock less than N greater than  are shown generated by a number of delay elements. The circuit 30 can be used to generate the clock signals Clock less than 1 greater than  to Clock less than N greater than  for the circuit 10. There is a practical limit to the maximum frequency of operation based on the delay time between the clock signals Clock less than 1 greater than  and Clock less than N greater than  due to the feedback to the input RB of the SR-latch.
A disadvantage of the circuit 30 is that the feedback to the latch has dependency on each delay element in the delay path. Before the next piece of data in the circuit can be processed, the SR-latch must be reset via the input RB. If the SR-latch is not reset via the input RB then the data can be lost at the output of the buffer across the terminator of the circuit 10 at higher frequencies but the amplitude can be maintained. FIG. 3 shows a timing diagram of the circuit 30 of FIG. 2. The data signal 11 is shown extending beyond the rising edge of the signal Clock less than N greater than  for proper operation.
It would be desirable to provide a method and/or architecture that may overcome SCSI cable induced effects by providing a controlled rise time and pre-compensation.
The present invention concerns an apparatus comprising a plurality of serially cascaded delay cells each configured to generate a phase of a multi-phase signal and an intermediate signal, where (i) each of the delay cells is generally configured to respond to a bias signal and one of the intermediate signals and (ii) a first of the delay cells is generally configured to respond to an input signal.
The objects, features and advantages of the present invention include providing a method and/or architecture for controlling the edge rate of low voltage signals that may (i) overcome SCSI cable induced effects, (ii) provide a controlled rise time and pre-compensation, (iii) increase the maximum operating frequency of a clock signal, (iv) reduce or eliminate delay cell interdependency, and/or (v) optimize driver circuit flip flop performance.